The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for minimizing memory array representations for enhanced synthesis and verification.
Logic designs used to represent hardware, software, or hybrid systems may be represented using a variety of formats. Example formats include hardware description languages (HDLs), higher-level languages such as SystemC, or lower-level formats such as netlists. There are numerous application domains in which it is advantageous to reduce the size of design representations. For example, logic synthesis and design aids often attempt to yield more compact representations that lend themselves to higher quality silicon or assembly code.
There are numerous application domains in which it is advantageous to reduce the size of memory array representations. For example, logic synthesis often attempts to yield more compact representations that lend themselves to higher-quality silicon or assembly code. Smaller array representations may directly factor into this goal, particularly for increasingly common intellectual property reuse and migration integrated circuit flows for which some aspects of a design may be irrelevant.
Decreasing the size of memory arrays also indirectly helps synthesis flows through helping simulation and verification flows, in that synthesis often requires the use of such algorithms during its processing. In particular, logic simulators often face substantial performance overheads in evaluating array ports, requiring hash table accesses to represent the contents of large arrays.
Hardware accelerators often have limitations on the number of arrays, and read/write port connectivity, that may be supported. Reducing array size may be mandatory to enable the application of acceleration. Formal verification techniques are often very sensitive to the size and number of ports. For example, techniques to use satisfiability solvers to analyze the behavior of arrays over time often directly compare the read address of each read port for a given time frame to the write address of every write port for every prior time frame. Such modeling entails quadratic complexity with respect to the number of read and write ports.